New storage lcass memeory and logic process imposes a range of challeneges for deposition, etch and CMP processes. On product, memory array cells have ~3x nm pitch and very high aspect ratio which makes yield killer defects undetectable, especially when deep in the memory cell trench. The standard optical inspection and e-beam inspection techniques are limited by the signal from these defects or the ability to accurately bin the defect to its source. In this presentation, we describe the application development of a hybrid e-beam based solution for characterizing two such challenging defects: 1) Deteciton of under etch defect in the trench area of the memory cell and 2) Detection of void in via in addition to characterizing the deformity of the vias as shown in Figure 1. And 2. respectively. Due to the physical size (<10nm) and buried nature of these defects, the optical signal from these defects is below the detection level or mixed deep into the nuisance population, and the standard e-beam based inpsection tools are unable to pinpoint the exact location of the defects in the array. In order to provide a solution to this problem, we use an e-beam based hot spot inspection technique such that targeted locations on the wafer can be imaged to provide high resolution SEM images of the defects. By combining a strong detection alogortihm and measuring attributes like grey level variation, defects can be quanitifed and binned. In case of under etch defects the unique grey level within the trench as shown in Figure 3. and darker grey level for voids in via as shown in Figure 4. are measured to flag the defective locations. A stable and repeatable recipe is setup to monitor lot to lot variation and also enable DOE studies for root cause analysis. Further, we explain some inspection and review challenges faced by the semicondcutor manufacturing industry with technology node shrinking. We present a smarter approach to close process gaps, improve cycle learning with a new iterative algorithm by combning e-beam and optical tools. The output of this scheme greatly improves the purity of inline results, more actionable pareto and accelerated learning to close process gaps.

Keywords: semicondcutor, yield, defect detection