We all see the growing use of semiconductor devices in all sectors of consumer products with the promise of being faster and smarter. For the last few decades, the advancement in semiconductor devices were driven by the increasing the number of transistors in an integrated circuit. While the effort on doubling transistors in an IC are still underway, we have seen this trend reach a plateau, and the associated processing cost increases exponentially. More recently, focus has moved on utilizing advanced integration to package devices with enhanced functionality, form factor, reduced power consumption, etc. The integration of devices, either 2.5D or 3D, are achieved by stacking devices through formation of metal redistribution layer (RDL) or through silicon vias (TSV’s). The creation of wafer level RDL/TSV for advanced integration scheme have challenges associated at each fabrication step. Here, we first discuss the electrodeposition process of copper suited for filling the different aspect ratio of RDL/TSV and optimize the electrodeposition process to achieve better uniformity during a key subsequent process at the chemical mechanical planarization step. The continued discussion will focus on how the stress builds up in a device with increasing metallization levels. Such stress in device arising from widely mismatched coefficient of thermal expansion of copper and substrate will result in wafer bow, warp and present challenges in downstream processing or integration. At last, a novel methodology is discussed on where the standard fabrication step fails, and an alternate processing step overcomes the stress and results in the desired final device structure.